Senior CPU Microarchitecture & Logic Design Engineer ​

Job Description:

We are seeking a Senior CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You will work closely with cross-functional teams to refine microarchitecture, develop RTL, and validate designs. This is an opportunity to work on challenging projects and play a key role in defining execution unit architecture for     next-generation CPU designs.

Responsibilities

• Define, develop, and refine microarchitecture specifications for complex CPU subsystems.
• Design and implement RTL to achieve targeted power, performance, area, and timing goals.
• Collaborate closely with the verification team to establish effective validation strategies for new designs.  
• Support test bench development and assist validation engineers in testing and debugging core and subsystem-level RTL in simulation, prototyping platforms, and silicon.
• Work with physical design teams to ensure that the design meets timing, area, reliability, testability, and power requirements.

Minimum Qualifications:​

• Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or a related field with 4+ years of experience; OR a Master’s degree with 3+ years of experience; OR a PhD with 1+ years of experience.
• Strong understanding of microprocessor architecture and microarchitecture.  
• Proficiency in applying trade-off and optimization techniques for performance, power, and area (PPA) in high-frequency design.
• Experience with SystemVerilog RTL development.
• Hands-on experience with front-end tools such as Verilog simulators, waveform viewers, linting tools, logic synthesis, and place-and-route.
• Programming skills in C/C++ and Python.
• Strong problem-solving skills and an analytical mindset.

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​Preferred Qualifications:

• Experience with one or more of the following areas:

• High performance branch prediction, instruction fetch, instruction decode, instruction caches

• Coherency protocols, memory consistency, L1/L2 caches, and TLBs design

• Out-of-order execution, including allocation, renaming, scheduling, and retirement.

• ALU, floating-point, and vector operations.