Meet The Leadership Team

Co-Founder, CEO, & President

Debbie Marr, PhD

Debbie Marr was an Intel Fellow and Chief Architect of the Advanced Architecture Development Group (AADG) at Intel, where she led development of a CPU core to bring leadership performance and perf/watt to Intel’s future platforms.

Prior to her current role, Debbie’s 33 years at Intel impacted both product and research. Debbie played leading roles on Intel CPU products from the 386SL to Intel’s current leading-edge products. Debbie was the server architect of Intel® Pentium™ Pro, Intel’s first Xeon Processor. She brought Intel Hyperthreading Technology from concept to product on the Pentium 4 Processor. She was the chief architect of the 4th Generation Intel Core™ (Haswell) and led advanced development for Intel’s 2017/2018 Core/Xeon CPUs. Debbie also spent 7 years in Intel Labs as the Director of Accelerator Architecture Lab where she led research in machine learning and acceleration techniques for CPU, GPU, FPGA, and AI Accelerators. Debbie has authored over 40 patents in many aspects of CPU, AI accelerators, and FPGA architecture/microarchitecture.

Debbie has a PhD in electrical and computer engineering from University of Michigan, an MS in electrical engineering and computer science from Cornell University, and a BS in electrical engineering and computer science from the University of California, Berkeley.

Co-Founder 

Jonathan Pearce

Jonathan Pearce was an Intel Principal Engineer, CPU Architect and a key technologist & strategist in the Advanced Architecture Development Group, encompassing power, performance, area, instruction set architecture, and microarchitecture concepts. ​​

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Jonathan contributed ​to both products and research during his 22 years at Intel. In product groups at Intel, Jonathan has worked in both pre-silicon and post-silicon roles on multiple generations of Intel Core™ SOCs. As an Intel research scientist, he was the liaison to the Intel Collaborative Research Institute for Computational Intelligence. He also led a proof-of-concept research project of a novel microprocessor architecture with breakthrough performance for AI/ML/HPC algorithms. Jonathan has authored over 19 patents in CPU, AI, and GPU architecture/microarchitecture. ​​

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Jonathan has an MS and a BS in electrical and computer engineering from Carnegie Mellon University.

Co-Founder

Srikanth Srinivasan, PhD

Dr. Srikanth Srinivasan (Sri) is an industry expert on microprocessor architecture and microarchitecture with over 20 years of technical leadership experience in product R&D. At Intel, he has successfully taped out several high performance chips (Nehalem, Haswell, Broadwell) used in client & server markets, as well as low-power chips (Bergenfield) used in phones & tablets. Most recently, Sri led the frontend and backend CPU teams at the Advanced Architecture Development Group in defining a novel microarchitecture that pushed the frontiers of processor performance. He has also worked on accelerators and computing-in-memory for AI. Sri is also a prolific author with more than a dozen highly cited papers and over 50 patents. His papers were featured in IEEE Micro Top Picks in 2003, 2004 and 2006.

Sri has a PhD in Computer Science from Duke University and a BE (Honors) in Computer Science from BITS Pilani. 

Co-Founder

Mark Dechene

Mark Dechene was an Intel Principal Engineer and CPU Architect in the Advanced Architecture Development Group, where he led the Memory Execution Architecture team within the CPU core.  In his 16 years at Intel, Mark has worked on architecture development for Intel CPU products including Haswell, Broadwell, Goldmont, Goldmont Plus, Tremont, and Skymont.  Throughout his career, Mark has focused on driving core product architecture teams to deliver leadership CPU performance.  Mark previously worked on product development at Motorola, in both Automotive Telematics and Cellular Telephone groups.  Mark has authored over 15 patents, focused on microprocessor performance.

Mark holds a MS in Computer Architecture from North Carolina State University (NCSU), and a BS in Electrical and Computer Engineering from Marquette University.  

Chief Commercial Officer

Lakshmi Mandyam

Lakshmi Mandyam is the Chief Commercial Officer at Ahead Computing, where she leads the company’s commercial strategy, driving growth through customer engagement, market expansion, and strategic partnerships. In this role, she oversees product management go-to-market execution, partner ecosystems, and business development initiatives that position Ahead Computing at the forefront of next-generation cloud and edge solutions.
Previously, Lakshmi was Vice President of Product Management and Partner Ecosystems for the Service Provider and Edge Cloud business at VMware. There, she guided the strategy and execution of VMware’s Telco Cloud portfolio, enabling service providers and MSOs to modernize infrastructure, deliver innovative edge services, and unlock new revenue streams. She also built and nurtured a global partner ecosystem, collaborating with OEMs, ISVs, and system integrators to drive adoption and customer success.
Before VMware, Lakshmi held leadership roles at Arm, where she led the Automotive and Server Systems & Ecosystems business, advancing Arm’s presence in server infrastructure and networking. She began her career with engineering, marketing, and management roles at Freescale Semiconductor and ColdWatt, contributing to enterprise technology innovation and scalable system solutions.
Lakshmi holds a Bachelor of Science degree in Electrical Engineering from the University of Texas at Austin. With more than two decades of experience spanning engineering, product management, and executive leadership, she is widely recognized for her ability to bridge deep technical expertise with commercial strategy, building ecosystems that accelerate innovation in a broad set of markets including cloud, telco, automotive, embedded and edge.

Vice President of Hardware Design 

Chung-lun Chan

Chung-lun Chan is a seasoned CPU designer and technical manager with over two decades of experience in frontend development of high-performance CPU cores, accelerators, and SoC systems. He has a proven track record of driving projects with complex design challenges to timely delivery. 

Throughout his career, Chung has led cross-site, cross-functional teams to achieve key milestones in Intel’s most advanced CPU and accelerator projects. He began his career in diverse roles, including Software Engineer, Architecture Validator, Execution Unit Designer, and Out-of-Order Cluster Designer. He established himself as a technical lead in the memory subsystem domain, earning six patents for his contributions. 

In his recent roles, Chung directed a cutting-edge accelerator project under the Exascale Computing Program, delivering major milestones ahead of schedule. As Director of the Advanced architecture Development Group, he played a pivotal role in building a multi-hundred-person design organization from the ground up, driving its success through strategic vision, technical expertise, and strong leadership. 

Chung holds a MS and BS in Computer Engineering from Oregon State University. 

Vice President of Design Verification

Alon Mahl

Alon Mahl is a seasoned expert in microprocessor verification with over 20 years of technical leadership in product R&D. During his tenure at Intel, Alon played a pivotal role in the successful tape-out of multiple high-performance Intel Core™ SoCs, including Skylake, Ivy Bridge, and Cannonlake, powering both client and server markets.

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In his most recent role at the Advanced Architecture Development Group, Alon led CPU verification teams, driving the development and verification of a groundbreaking high-performance CPU microarchitecture.

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Alon expertise extends to autonomous driving, where he led the verification of cutting-edge accelerators at Mobileye.

Alon holds a Bachelor of Science in Electrical Engineering from the Technion – Israel Institute of Technology.

México Country General Manager

Leonel Haro

Leonel (Leo) Haro is a seasoned leader in both industry and academia, with over 15
years of experience developing semiconductor pre-silicon verification and logic design
talent in Guadalajara, Mexico’s Silicon Valley. Leo has a proven track record in
development of world-class cutting-edge semiconductor technologies.

Leo contributed to key advancements in microarchitecture and design for Intel’s
memory controllers, particularly for hardware-based DRAM training algorithms across
multiple DDRx/LPDDRx generations, high-level SoC flows for Intel Graphics IP, and
successfully drove SoCs to PRQ for Intel’s Optane 3DXP technology controllers. In his
most recent role, Leo led a highly skilled team of CPU Core verification and designers in
Intel’s Advanced Architecture Development Group—marking a significant milestone for
the region.

In addition to his industry contributions, Leo is a dedicated educator, currently serving
as a part-time professor at ITESO. His teaching portfolio includes Digital Systems, Logic
Design, Computer Architecture, FPGAs, Microcontrollers, and Electronics, shaping the
next generation of engineers.

Leo holds a Master’s in Electronic Design with a minor in Integrated Circuit Design from
ITESO and a BS in Electrical Engineering from ITESM.