About the Role
You will shape the observability, diagnosability, andbring-up readiness of our high-performance RISC-V CPU designs from pre-siliconarchitecture through first-silicon validation and production support.
The role combines hands-on RTL implementation with technical leadership across architecture, design, validation, firmware, software, and DFT. You will help establish the debug standards, infrastructure, and feedback loops that make complex silicon easier to bring up, analyze, and improve.
What You'll Do
Defineand build debug architecture
· Define debug and trace architecture for newsilicon programs, including on-chip instrumentation, trace strategy, accesstopology, and bring-up readiness.
· Architect and implement on-chip debug featuressuch as embedded logic analyzers, trace buffers, trigger logic, debug busfabrics, performance counters, and error-injection hooks.
· Design debug access infrastructure for complex multi-core, multi-die, and chiplet-based systems, including JTAG, traceinterfaces, and custom debug ports where needed.
· Establish and champion design-for-debugpractices across the organization.
Enablefaster bring-up and root-cause analysis
· Apply hands-on post-silicon bring-up experienceto define practical pre-silicon debug requirements.
· Support post-silicon validation by guiding debugstrategy, interpreting trace data, and diagnosing silicon anomalies.
· Lead or support root-cause analysis of hardwareissues using logic analyzer traces, scan dumps, on-chip instrumentation, andrelated debug data.
· Translate post-silicon lessons learned intostronger architecture, implementation practices, and debug methodology forfuture tape-outs.
Collaborateacross the stack
· Partner closely with verification, DFT, firmware, and software teams to ensure debug features are practical, validated pre-silicon, and effective in the lab.
· Work with EDA partners and IP vendors toevaluate and integrate third-party debug IP and tools.
· Influence SoC-level architecture decisions toensure sufficient debug bandwidth, visibility, and access across clock andpower domains.
· Contribute to internal debug tooling,automation, documentation, and bring-up playbooks that improve team-wide debugefficiency.
Required Qualifications
· Bachelor's or Master's degree in ElectricalEngineering, Computer Engineering, or a related field.
· 8+ years of experience in silicon design,silicon validation, post-silicon debug, or a closely related discipline.
· Demonstrated experience defining debugarchitecture, designing debug features, or implementing silicon debuginfrastructure.
· Strong hands-on post-silicon debug experience,including chip bring-up, scan dumps, logic analyzers, and diagnosis of realsilicon failures.
· Deep knowledge of debug and trace standards andprotocols such as ARM CoreSight, IEEE 1149.1 JTAG, the RISC-V DebugSpecification, or equivalent proprietary architectures.
· Proficiency in RTL design usingVerilog/SystemVerilog, with experience implementing debug logic that has beenfabricated and validated in silicon.
· Strong understanding of SoC architecture,including interconnects, power domains, clock-domain crossings, and memorysubsystems.
· Ability to work effectively across hardwaredesign, validation, firmware, software, and DFT teams.
Preferred Qualifications
· Experience defining debug architecture for ARMNeoverse/CSS-based or RISC-V-based SoCs.
· Experience with multi-die or chiplet-basedsystems and the associated debug and observability challenges.
· Familiarity with die-to-die interconnectstandards such as UCIe.
· Background in embedded trace analysis,performance profiling, or system-level trace correlation.
· Experience building automation for debugworkflows using Python, Tcl, or similar scripting languages.
· Understanding of adjacent DFT concepts such asscan compression, ATPG, and BIST, and how they interact with debuginfrastructure.
· Experience working with third-party debug IPproviders or EDA vendors to define requirements and integrate solutions.
What Success Looks Like
· Clear, scalable debug architecturespecifications for new silicon programs.
· Production-ready debug and trace RTL thatimproves observability without compromising area, power, or performancetargets.
· Bring-up guides and debug playbooks thataccelerate post-silicon validation.
· Ongoing enhancements to debug methodology drivenby real post-silicon experience and feedback loops.
Why This Role Is Compelling
· You will help define debug architecture early,when it has the greatest impact on first-silicon success.
· You will influence how debug is built across IP, SoC, and chiplet programs rather than working in a narrow post-silicon-onlyscope.
· You will pair architecture-level ownership withhands-on implementation and lab relevance, creating a high-leverage role for anexperienced debug leader.