SoC Design Verification Lead

Responsibilities

Verification

• RISC-V TSO Compliance: Develop and execute verification plans to confirm RISC-V Total Store Ordering (TSO) compliance, coordinated with the NOC verification environment. Ensure memory ordering guarantees are maintained across all coherent agents and traffic scenarios.

• CHI Protocol Verification: Verify that optional and configurable features of the AMBA CHI specification behave as expected across all supported operating modes. Define coverage models and directed tests for CHI transaction flows, snoop filters, and cache state transitions.

• Linux Boot Validation: Drive the SoC verification environment to the point where Linux boot completes successfully in emulation. Own the bring-up checklist and triage boot failures across CPU, interconnect, memory, and peripheral subsystems.

• Firmware Readiness: Coordinate with the firmware team to ensure firmware readiness, including meeting code coverage thresholds, integrating required patches, and validating firmware-driven initialization sequences in the DV environment.

• Debug & Trace Infrastructure: Verify debug, trace, and run control functionality end-to-end. Ensure JTAG, CoreSight trace, and debug access ports operate correctly and meet specification requirements.

• CSR & Interrupt Verification: Validate CSR read/write behavior across all cores, including core-to-core CSR access, APPLIC (Advanced Platform-Level Interrupt Controller) behavior, and interrupt routing and prioritization in simulation.

• Performance Validation

• Develop performance testbenches and regression infrastructure to measure and validate key system metrics against architectural targets, including LLC hit latency (co-located vs. far home nodes), DRAM access latency under representative traffic patterns, LLC read bandwidth with all cores enabled, and bandwidth to PCIe-attached devices under sustained and burst scenarios. Correlate simulation results against architectural reference models and flag regressions.

• Correlation & Compliance

• Model Correlation: Execute correlation runs on small representative workloads. Compare RTL simulation results against architectural reference models and document any discrepancies.

• Architectural Compliance: Run architectural and specification compliance binaries (e.g., RISC-V architectural test suites, AMBA CHI protocol compliance tests) and confirm all tests pass. Own the compliance sign-off process.

Verification Strategy & Leadership

• Verification Planning: Define the overall SoC verification strategy, with emphasis on emulation and FPGA prototyping workflows, including methodology selection (emulation test plans), coverage closure plans, and regression management.

• Team Leadership: Build, mentor, and manage a DV team. Assign workstreams, track progress, and drive the team toward tape-out readiness milestones.

• Vendor Coordination: Interface with external IP vendors on IP-level verification deliverables, integration test plans, and bug resolution.

• Bug Triage & Resolution: Own the bug tracking and triage process. Prioritize issues by severity and silicon risk and drive timely resolution with design and architecture teams.

Qualifications & Skills

Minimum Qualifications

• Graduate degree (MS or PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field

• 10+ years of relevant industry experience in SoC/ASIC design verification, with at least 3 years in a lead or management role

• Deep expertise in UVM/SystemVerilog verification methodology

• Strong understanding of SoC architecture, on-chip interconnects, and memory subsystems

• Experience developing and executing verification plans for complex multi-core SoCs

• Proven ability to drive functional coverage closure and sign-off on tape-out readiness

• Excellent written and verbal communication skills for interfacing with IP vendors, design partners, and internal stakeholders

• Ability to work independently and drive technical decisions in a fast-paced startup environment

Preferred Qualifications

• RISC-V Verification: Direct experience verifying RISC-V CPU cores or subsystems, including ISA compliance testing, memory ordering (TSO/RVWMO), and privilege mode transitions

• AMBA CHI Expertise: Hands-on verification experience with AMBA CHI or ACE protocols, including coherent interconnect verification, snoop filter behavior, and cache coherency scenarios

• Performance Verification: Experience building performance verification environments, including latency and bandwidth measurement infrastructure and model correlation flows

• Emulation & FPGA Prototyping: Direct experience with Siemens Veloce emulation platforms and/or proFPGA prototyping systems for SoC-level validation, performance benchmarking, and software bring-up. Ability to develop and maintain emulation test environments and debug flows.

• Firmware Co-Verification: Experience coordinating firmware and hardware verification, including bare-metal test development and firmware-driven DV flows

• Scripting & Automation: Proficiency in Python, Perl, or similar languages for test generation, regression infrastructure, and results analysis

‍What We Offer

• Competitive Compensation & Benefits Package

• Technical Leadership Opportunity

• Collaboration with talented engineers passionate about cutting-edge CPU technologies

• Work on advanced chiplet-based architectures using the most advanced semiconductor process nodes and packaging technologies available

• Opportunities for professional growth in an innovative startup environment

• A flexible and inclusive work culture based in Portland, OR