Lead CPU Microarchitecture & Logic Design Engineer, Fetch and Decode 

​Location: Portland, OR or Austin, TX

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Job Description

We are seeking a talented Senior Staff CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance CPU subsystems, with a focus on achieving optimal power, performance, and area (PPA). You will work closely with cross-functional teams to develop innovative solutions, refine microarchitecture, and validate designs. This is an opportunity to work on cutting-edge projects and make a significant impact on the future of CPU technology in a collaborative and fast-paced environment.

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Responsibilities

• Define, develop, and drive microarchitecture specifications for complex CPU subsystems with a focus on Branch Prediction, Instruction Fetch, and Instruction Decode. 

• Collaborate closely with the verification team to establish effective verification strategies for new designs. Support testbench development and assist verification engineers in testing and debugging core and subsystem-level RTL in simulation, prototyping platforms, and silicon. 

• Front-end RTL design and optimization to achieve power, performance, area, and timing objectives. 

• Coordinate with core-wide and cross-discipline engineering teams to implement RTL in physical design, ensuring adherence to layout, reliability, interface behavior, and testability requirements. 

• Provide technical leadership, mentoring junior engineers and contributing to long-term CPU core architecture roadmaps.  

• Create and effectively communicate technical details to team members. 

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Qualifications & Skills:​

• Minimum Qualifications:​​

  • 10+ years of experience in CPU microarchitecture and RTL design. 

  • Extensive experience with high-performance instruction fetch, branch prediction, instruction decode, and instruction caches. 

  • In-depth knowledge of microprocessor frontend architecture and microarchitecture, including expertise in optimization techniques and trade-offs between performance, power, and area (PPA). 

  • The ability to anticipate difficulties in physical design realities and rapidly adapt to evolving circumstances. 

  • Strong proficiency in SystemVerilog and hardware design methodologies. 

  • Expert experience with front-end tools such as Verilog simulators and emulators, waveform viewers, logic synthesis, and place-and-route. 

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• Preferred Qualifications:​

  • Expertise with rapid instruction fetch, highly accurate branch prediction, and high bandwidth instruction decoding for allocation. 

  • A deep technical background encompassing prediction algorithms and structures, prefetching, and accelerated flush/clear recovery. 

  • Familiarity with RISC-V ISA and major extensions. 

  • Ability to influence and define work models, coding standards, and design methodologies for large-scale CPU projects.  

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What We Offer:

• Competitive salary and benefits package.

• Opportunities for professional growth in an innovative startup environment.

• Collaboration with talented engineers passionate about cutting-edge CPU technologies.

• A flexible and inclusive work culture based in Portland, OR or Austin, TX.​​​​

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