Lead CPU Microarchitecture & Logic Design Engineer, Out-of-Order Execution 

​Location: Portland, OR or Austin, TX

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Job Description

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We are seeking a talented Senior Staff CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance CPU subsystems, with a focus on achieving optimal power, performance, and area (PPA). You will work closely with cross-functional teams to develop innovative solutions, refine microarchitecture, and validate designs. This role offers the opportunity to contribute directly to the development of high-performance CPU cores, working on advanced microarchitecture innovations in a highly collaborative and fast-moving environment.

 

Responsibilities

• Define, develop, and refine microarchitecture specifications for complex CPU subsystems, with a focus on Out-of-Order execution and retirement. 

• Drive RTL design and implementation, balancing complex interactions between execution, commit, and backend structures while ensuring correctness and efficiency. 

• Design and implement RTL to achieve targeted power, performance, area, and timing goals. 

• Collaborate closely with the verification team to establish effective validation strategies for new designs. Support test bench development and assist validation engineers in testing and debugging core and subsystem-level RTL in simulation, prototyping platforms, and silicon. 

• Work with cross-functional engineering teams to ensure that the design meets timing, area, reliability, testability, and power requirements. 

• Analyze backend data to debug and improve timing, area, and power issues, identifying opportunities for architectural optimizations and improvements. 

• Provide technical leadership, mentoring junior engineers and contributing to long-term CPU core architecture roadmaps. 

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Qualifications & Skills:​

• Minimum Qualifications:​​

  • 10+ years of experience in CPU microarchitecture and RTL design, with a focus on out-of-order execution. 

  • Deep understanding of instruction commit, register reclaim, precise exceptions, and speculation recovery mechanisms. 

  • Strong proficiency in SystemVerilog and hardware design methodologies. 

  • Ability to drive microarchitecture decisions, trade-off analyses, and optimization strategies. 

  • Experience with performance modeling, power analysis, and timing closure in high-frequency designs. 

  • Hands-on experience with debugging RTL in simulation and emulation environments. 

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• Preferred Qualifications:​

  • Familiarity with checkpointing, recovery mechanisms, and memory consistency models. 

  • Knowledge of RISC-V instruction set, including privileged ISA, faults, exception, and interrupt semantics 

  • Ability to influence and define work models, coding standards, and design methodologies for large-scale CPU projects. 

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What We Offer:

• Competitive salary and benefits package.

• Opportunities for professional growth in an innovative startup environment.

• Collaboration with talented engineers passionate about cutting-edge CPU technologies.

• A flexible and inclusive work culture based in Portland, OR or Austin, TX.​​​​​​​​

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